Unified Fabric: The Future of AI Data Center Connectivity

Performance gains in AI processors have shifted the network bottleneck from compute to connectivity. The data center’s network fabric—the high-speed communication infrastructure of switches, optics and cabling that connects processors, accelerators and memory—has now emerged as the critical constraint on scaling AI networks. Today's high-performance data centers rely on a patchwork of specialized interconnect technologies such as PCIe, NVLink, Ethernet and the emerging Compute Express Link (CXL). Each excels within its domain, but stitching these protocols together introduces latency, power inefficiencies and management complexity that limit overall system performance.

The industry's answer is a unified fabric architecture: a vision of converged connectivity that treats the entire data center as a single, coherent compute system. This shifts the critical engineering challenge from software orchestration to the physical layer. Connectors, optics and cabling must now handle massive data volumes, signal integrity and thermal demands that come with AI-scale computing.

Today's AI data center connectivity strategy is a collection of specialized protocols where the whole delivers less efficiency than the sum of its parts. Each protocol—from PCIe and NVLink to Ethernet and CLX—is optimized for its own domain, but data must traverse multiple layers to move between compute, memory and storage resources. Every transition introduces latency, buffering and translation overhead that collectively throttle AI training performance and leave valuable compute resources underutilized.

The specific limitations of each interconnect highlight the challenges of heterogeneous AI fabrics. NVLink delivers exceptional GPU-to-GPU bandwidth within a server but does not natively scale across nodes. Ethernet and InfiniBand provide the required rack-to-rack and cluster connectivity, yet their protocol stacks and CPU-driven data handling introduce significant software overhead and latency penalties compared to native GPU fabrics. PCIe and the emerging CXL standard offer versatility for peripherals and memory, but they function primarily as specialized extensions for specific tasks rather than high-bandwidth GPU communication.

The industry's vision for solving the patchwork problem is the unified fabric: a design that converges multiple specialized protocols into a single, high-performance network for AI-critical data traffic. The guiding principle is radical simplification. Rather than maintaining separate domains for PCIe, NVLink and Ethernet, a unified fabric creates a flat, composable network that seamlessly carries compute, storage and memory traffic across the data center. This architecture materializes the “SuperNode” concept, which treats the entire cluster as a dynamically reconfigurable resource pool. In this model, a GPU in one rack can directly access memory in another with minimal overhead; storage traffic is consolidated into the same high-performance fabric, and compute resources can be dynamically reconfigured to maximize utilization.

Multiple major industry initiatives are advancing this vision. These range from specific vendor proposals like Huawei’s UB-Mesh, which aims for more than 10Tbps of bandwidth per ASIC with sub-microsecond latency, to broader collaborative efforts like the Ultra Ethernet Consortium. The tangible outcomes directly address the inefficiencies of the current patchwork approach: significantly lower latency accelerates large-scale AI training, simplified infrastructure reduces operational overhead and dynamic resource allocation minimizes idle or underutilized hardware.

While the unified fabric is a powerful protocol concept, its implementation shifts the primary engineering challenge to the physical layer, imposing a new class of demands across the entire interconnect path:

• On-Chip I/O: The massive bandwidth requirements drive the adoption of co-packaged optics (CPO), where the optical transceiver is integrated directly next to the processor. This presents new engineering challenges in thermal management, power delivery and serviceability.
• Internal Signal Path: Routing 224Gbps-PAM-4 signals across a conventional PCB can become a critical bottleneck, as the high data rates introduce signal degradation and impair overall systems performance.
• Rack-Level Connectivity: To scale fabrics across thousands of nodes, data centers need advanced pluggable connectors with ultra-dense cabling that can reliably handle 1.6Tb/port while maintaining signal integrity.

Beyond the hardware, a next-generation fabric must address challenges in ecosystem adoption, compatibility with existing standards and maintaining vendor neutrality.

Meeting the physical demands of a unified fabric requires an engineering approach that considers the entire interconnect path. As a key contributor to the Open Compute Project (OCP), Molex helps shape the open standards for next-generation hardware and provides a portfolio of solutions for the massive data loads, thermal challenges and density requirements of this new architecture. 

On-Chip I/O Density and Thermals
The move to CPO introduces critical challenges in managing heat and improving field serviceability. The Molex External Laser Source Interconnect System (ELSIS) is a complete, pluggable solution that moves the laser off the processor substrate. This approach uses a blind-mating design, which improves thermal performance, simplifies maintenance and enhances system safety by removing user access to optical fibers.

Internal Signal Integrity
Routing 224Gb-PAM-4 signals across a traditional PCB creates a major internal bottleneck due to signal degradation. BiPass technology delivers a direct-to-I/O solution, routing high-speed signals through dedicated low-loss twinax cables that bypass the PCB. This preserves data integrity and can eliminate the need for costly, power-hungry retimers, reducing both system cost and thermal load. 

Rack-Level Connectivity
Scaling the fabric across thousands of nodes demands a new generation of I/O ports for 1.6Tb+ speeds and extreme density. A portfolio of QSFP-DD and OSFP pluggable connectors deliver the essential industry-standard, high-density interfaces. These solutions offer robust, high-bandwidth connections while providing distinct advantages like the backward compatibility of QSFP-DD and the superior thermal management of the OSFP form factor.